Integer multiplication and division operations are generally some of the most costly operations in modern processors, as multiplication and division operations usually have the longest execution times among all basic integer arithmetic operations. To reduce execution time for single-cycle multiplication operations with high-radix Booth encoders, current systems typically rely on Wallace/Dadda tree implementations that incorporate a final adder. Although division operations are usually less common than addition and multiplication operations, there are many important areas that utilize division operations such as rendering systems, artificial intelligence, algorithms, data compression, etc.
Using a larger basis for the division on the basis of repetition is one way to accelerate the operation of division, but this approach increases the complexity of hardware implementation and, consequently, leads to an increase in footprint, power consumption and price/performance ratio. To date, there have been a number of approaches to implementing division on a large scale, but aspects of these implementations remain unexplored, particularly with regard to effective area and power consumption concerning overflow situations.
Current systems generally use separate lines and, in some cases, separate components for multiplication operations than they do for division operations. Such arrangements can be problematic, particularly with regard to the individual and/or total footprint, i.e., physical area, that is required by the components used in the design. Further, the power consumption of the components is often significant.